Pipelined hierarchical architecture for high performance packet classification

Basit Öğe Kaydı
dc.authorwosiderdem, oğuzhan/AAG-6229-2019
dc.contributor.authorErdem, Oguzhan
dc.date.accessioned2024-06-12T11:11:56Z
dc.date.available2024-06-12T11:11:56Z
dc.date.issued2016
dc.departmentTrakya Üniversitesien_US
dc.description.abstractHierarchical search structures satisfying good memory and update performance demands, are encouraging solution for packet classification in multi-core processors. However, pipelined hardware implementation of these algorithms has two major issues: (1) backtracking which causes stalling the pipeline and (2) memory inefficiency owing to variation in the size of trie nodes. In this paper, we present a clustering algorithm named recursive leaf extraction (RLE) that partitions an input ruleset into a certain number of sub-rulesets to eradicate backtracking in hierarchical search structures. We further enhanced RLE method and proposed Optimized-RLE (O-RLE) algorithm to balance the size of clusters. Additionally, we present a ternary trie data structure (T-epsilon) that takes the advantage of epsilon-branch property to segment large trie nodes into fixed size epsilon-nodes to solve the memory inefficiency problem. We propose two hierarchical data structures denoted Tree-Trie(epsilon) (TT epsilon)and its extended version Tree-Trie(epsilon)-Linked List (TT epsilon L). TT epsilon consists of a binary search tree in Stage 1 and multiple T-epsilon structures in Stage 2. TT epsilon L comprises an additional linked-list (LL) data structure in Stage 3 that maintains the large portion of a nodes and thus freely optimizes search delay with a significant improvement in memory efficiency (20.39 bytes/rule). To accommodate the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs) (134 Gbps). (C) 2016 Elsevier B.V. All rights reserved.en_US
dc.identifier.doi10.1016/j.comnet.2016.04.009
dc.identifier.endpage164en_US
dc.identifier.issn1389-1286
dc.identifier.issn1872-7069
dc.identifier.scopus2-s2.0-84964607546en_US
dc.identifier.scopusqualityQ1en_US
dc.identifier.startpage143en_US
dc.identifier.urihttps://doi.org/10.1016/j.comnet.2016.04.009
dc.identifier.urihttps://hdl.handle.net/20.500.14551/22984
dc.identifier.volume103en_US
dc.identifier.wosWOS:000378438200011en_US
dc.identifier.wosqualityQ1en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.relation.ispartofComputer Networksen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectPacket Classificationen_US
dc.subjectPacket Forwardingen_US
dc.subjectFPGAen_US
dc.subjectPipelineden_US
dc.subjectScalable High-Throughputen_US
dc.titlePipelined hierarchical architecture for high performance packet classificationen_US
dc.typeArticleen_US

Dosyalar

Koleksiyon

WoS İndeksli Yayınlar Koleksiyonu
Scopus İndeksli Yayınlar Koleksiyonu