Multi-pipelined and memory-efficient packet classification engines on FPGAs

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dc.authorwosiderdem, oğuzhan/AAG-6229-2019
dc.contributor.authorErdem, Oguzhan
dc.contributor.authorCarus, Aydin
dc.date.accessioned2024-06-12T11:11:56Z
dc.date.available2024-06-12T11:11:56Z
dc.date.issued2015
dc.departmentTrakya Üniversitesien_US
dc.description.abstractA packet classification task incorporated in network firewalls to recognize and sift threats or unauthorized network accesses is accomplished by checking incoming packet headers against a pre-defined filter set. Plenty of solutions to reduce the memory requirement of filter set storage and accommodate packet classification to line rates have been proposed over the past decade. Among all the existing approaches, hierarchical data structures maintain great memory performance however their hardware realization suffers from two issues: (i) backtracking and (ii) memory inefficiency. In this paper, we propose two data structures denoted range tree-linked list hierarchical search structure (RLHS) and value-coded trie structure with epsilon-branch property (VC epsilon) for packet classification. RLHS resolves backtracking by exploiting range tree in Stage 1 and linked list data structure in Stage 2 overcomes the memory inefficiency. VC epsilon trie that naturally does not involve backtracking problem, solves memory inefficiency issue by comprising a fixed size bin at each node. Apart from conventional binary trie, a new rule is inserted into the first available bin on the path of this rule in a VC epsilon trie, and epsilon-branch property is utilized in case all the bins are full. We also propose a rule categorization algorithm that partitions an input ruleset by considering the field features of rules to minimize the memory requirement. To support the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs). (C) 2015 Elsevier B.V. All rights reserved.en_US
dc.identifier.doi10.1016/j.comcom.2015.05.017
dc.identifier.endpage91en_US
dc.identifier.issn0140-3664
dc.identifier.issn1873-703X
dc.identifier.scopus2-s2.0-84939569105en_US
dc.identifier.scopusqualityQ1en_US
dc.identifier.startpage75en_US
dc.identifier.urihttps://doi.org/10.1016/j.comcom.2015.05.017
dc.identifier.urihttps://hdl.handle.net/20.500.14551/22983
dc.identifier.volume67en_US
dc.identifier.wosWOS:000361162500008en_US
dc.identifier.wosqualityQ1en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherElsevier Science Bven_US
dc.relation.ispartofComputer Communicationsen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectPacket Classificationen_US
dc.subjectFPGAen_US
dc.subjectPipelineen_US
dc.subjectTrieen_US
dc.subjectArchitectureen_US
dc.titleMulti-pipelined and memory-efficient packet classification engines on FPGAsen_US
dc.typeArticleen_US

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