Simple CART Based Real-Time Traffic Classification Engine on FPGAs

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dc.authorwosiderdem, oğuzhan/AAG-6229-2019
dc.authorwosidSOYLU, Tuncay/HHN-7426-2022
dc.authorwosidSOYLU, Tuncay/R-1857-2019
dc.contributor.authorSoylu, Tuncay
dc.contributor.authorErdem, Oguzhan
dc.contributor.authorCarus, Aydin
dc.contributor.authorGuner, Edip S.
dc.date.accessioned2024-06-12T11:20:02Z
dc.date.available2024-06-12T11:20:02Z
dc.date.issued2017
dc.departmentTrakya Üniversitesien_US
dc.descriptionInternational Conference on Reconfigurable Computing and FPGAs (ReConFig) -- DEC 04-06, 2017 -- Cancun, MEXICOen_US
dc.description.abstractTraffic classification is a process which assorts computer network traffic into predefined traffic classes by utilizing packet header information or network packet statistics. Real-time traffic classification is mainly used in network management tasks comprising traffic shaping and flow prioritization as well as in network security applications for intrusion detection. Machine Learning (ML) based traffic classification that exploits statistical characteristics of traffic, has come into prominence recently, due to its ability to cope with encrypted traffic and newly emerging network applications utilizing non-standard ports to circumvent firewalls. To meet high data rates and achieve online classification with ML-based techniques, Field Programmable Gate Arrays (FPGAs) providing abundant parallelism and high operating frequency is the most appropriate platform. In this paper, we propose to use Simple Classification and Regression Trees (Simple CART) machine learning algorithm for traffic classification. However, the variations in node sizes of Simple CART decision tree caused by discretization pre-process incur memory and resource inefficiency problems when the tree is directly mapped onto the hardware. To resolve these problems, we propose to represent Simple CART decision tree by two stage hybrid data structure (Extended-Simple CART) that comprises multiple range trees in Stage 1 and a Simple CART decision tree enriched with bitmaps at its nodes in Stage 2. Our design is implemented on parallel and pipelined architectures using Field Programmable Gate Arrays (FPGAs) to acquire high throughput. Extended-Simple CART architecture can sustain 557 Gbps or 1741 million classification per second (MCPS) (for the minimum packet size of 40 Bytes) on a state-of-the-art FPGA and achieve an accuracy of 96.8% while classifying an internet traffic trace including eight application classes.en_US
dc.description.sponsorshipNatl Inst Astrophy Opt & Elect Mexico,Virginia Tech,Univ N Carolina Charlotte,IEEE,IEEE Circuits & Syst Soc,XILINXen_US
dc.identifier.isbn978-1-5386-3797-5
dc.identifier.issn2325-6532
dc.identifier.scopus2-s2.0-85046952620en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.urihttps://hdl.handle.net/20.500.14551/25438
dc.identifier.wosWOS:000426529700042en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartof2017 International Conference On Reconfigurable Computing And Fpgas (Reconfig)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectSupport Vector Machinesen_US
dc.subjectNetworksen_US
dc.titleSimple CART Based Real-Time Traffic Classification Engine on FPGAsen_US
dc.typeConference Objecten_US

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