Bit vector-coded simple CART structure for low latency traffic classification on FPGAs

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dc.authoridSOYLU, TUNCAY/0000-0001-7595-8879
dc.authorwosiderdem, oğuzhan/AAG-6229-2019
dc.authorwosidSOYLU, Tuncay/HHN-7426-2022
dc.contributor.authorSoylu, Tuncay
dc.contributor.authorErdem, Oguzhan
dc.contributor.authorCarus, Aydin
dc.date.accessioned2024-06-12T11:16:33Z
dc.date.available2024-06-12T11:16:33Z
dc.date.issued2020
dc.departmentTrakya Üniversitesien_US
dc.description.abstractTraffic classification is the determination of the application types during real-time flow of internet traffic. Machine learning (ML) based classification approaches that can classify internet traffic using statistical properties of flows are of great interest, due to its ability to work under encrypted traffic conditions. In this paper, we propose a novel data structure, named Bit Vector Coded Simple CART (BC-SC), for ML based internet traffic classification. BC-SC data structure is a scalable solution in terms of the number of application classes while providing a significant improvement in search latency, memory requirement and throughput when compared to the state-of-the-art approaches. We also designed two alternative hardware architectures, namely Pipelined and Discrete Parallel Range Comparators (DPRC)-based, on the Field Programmable Gate Array (FPGA) platform to support BC-SC data structure. Pipelined and DPRC-based architectures can achieve up to 665 and 914 giga bit per second (Gbps) or 2078 and 2857 million classifications per second (MCPS) respectively for the minimum packet size of 40 Byte. Furthermore, the proposed engines both can reach 96.8125% accuracy with eight application classes. (C) 2019 Elsevier B.V. All rights reserved.en_US
dc.identifier.doi10.1016/j.comnet.2019.106977
dc.identifier.issn1389-1286
dc.identifier.issn1872-7069
dc.identifier.scopus2-s2.0-85075313928en_US
dc.identifier.scopusqualityQ1en_US
dc.identifier.urihttps://doi.org/10.1016/j.comnet.2019.106977
dc.identifier.urihttps://hdl.handle.net/20.500.14551/24366
dc.identifier.volume167en_US
dc.identifier.wosWOS:000510524600008en_US
dc.identifier.wosqualityQ1en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.relation.ispartofComputer Networksen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectTraffic Classificationen_US
dc.subjectMachine Learningen_US
dc.subjectSimple CARTen_US
dc.subjectHigh Throughputen_US
dc.subjectLow Latencyen_US
dc.subjectFPGAen_US
dc.subjectData Structureen_US
dc.subjectNetworksen_US
dc.titleBit vector-coded simple CART structure for low latency traffic classification on FPGAsen_US
dc.typeArticleen_US

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