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Öğe Large-scale SRAM-based IP lookup architectures using compact trie search structures(Pergamon-Elsevier Science Ltd, 2014) Erdem, Oguzhan; Carus, Aydin; Le, HoangSRAM-based pipelined architectures for high-speed IP lookup using Field Programmable Gate Arrays (FPGAs) has recently attracted a great deal of attention from researchers. Due to the limited amount of on-chip memory and the number of I/O pins of FPGAs, compact data structures providing high memory efficiency are in great demand. In IP lookup, a binary trie that is an ordered tree data structure is used to store the routing table entries. In this paper, we propose two compact trie structures denoted Compact Trie Forest (CTF) and Compact Trie(c) (CTc) for Internet Protocol (IP) lookup. The large variant in node sizes leading to the memory inefficiency in hardware implementation is resolved by using multiple disjoint pipelines in CTF. CTc solves the problem within a single pipeline by splitting large nodes into sequentially connected multiple small and fixed size nodes. To support each data structure, two pipelined SRAM-based architectures optimized by allowing multiple memory banks in each stage are also proposed. (C) 2013 Elsevier Ltd. All rights reserved.Öğe Value-Coded Trie Structure for High-Performance IPv6 Lookup(Oxford Univ Press, 2015) Erdem, Oguzhan; Carus, Aydin; Le, HoangDynamically updateable and memory-efficient search structures for Internet protocol (IP) lookup have lately attracted a great deal of attention from the researchers. In this paper, we focus on the next-generation IPv6 routing protocol comprising large and sparsely distributed routing tables. The existing data structures either suffer from inefficient resource and memory usage (trie-based algorithms), or require complicated construction processes such as converting routing prefixes into their longer representatives and sorting (tree-based algorithms), or both. We propose a novel data structure denoted value-coded trie (VC-trie) for IP lookup. VC-trie provides significant memory saving in comparison with that of the existing solutions in both IPv4 and IPv6 domains. Thereby, our structure can support longer prefix lengths and larger routing tables. We also design an static random access memory (SRAM)-based pipelined architecture to assist the VC-trie structure to improve the throughput. The architecture is implemented utilizing a state-of-the-art field programmable gate array (FPGA) device and sustainable throughput of 448 million lookups per second (with a routing table consisting of 324K prefixes) is achieved. Furthermore, the architecture can be enhanced with external SRAMs to relax the limitations of the existing FPGA device in on-chip memory.