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Bit vector-coded simple CART structure for low latency traffic classification on FPGAs
(Elsevier, 2020) Soylu, Tuncay; Erdem, Oguzhan; Carus, Aydin
Traffic classification is the determination of the application types during real-time flow of internet traffic. Machine learning (ML) based classification approaches that can classify internet traffic using statistical properties of flows are of great interest, due to its ability to work under encrypted traffic conditions. In this paper, we propose a novel data structure, named Bit Vector Coded Simple CART (BC-SC), for ML based internet traffic classification. BC-SC data structure is a scalable solution in terms of the number of application classes while providing a significant improvement in search latency, memory requirement and throughput when compared to the state-of-the-art approaches. We also designed two alternative hardware architectures, namely Pipelined and Discrete Parallel Range Comparators (DPRC)-based, on the Field Programmable Gate Array (FPGA) platform to support BC-SC data structure. Pipelined and DPRC-based architectures can achieve up to 665 and 914 giga bit per second (Gbps) or 2078 and 2857 million classifications per second (MCPS) respectively for the minimum packet size of 40 Byte. Furthermore, the proposed engines both can reach 96.8125% accuracy with eight application classes. (C) 2019 Elsevier B.V. All rights reserved.
Classification of Parkinson's Disease Using Dynamic Time Warping
(IEEE, 2019) Kurt, Ilke; Ulukaya, Sezer; Erdem, Oguzhan
Deteriorations in handwriting or in basic shape sketching are one of the most referenced symptoms for early diagnosis of Parkinson's disease (PD). For this reason, the design of a fair, trustworthy and efficacious Computer-aided Diagnosis (CAD) model has supportive importance for the early diagnosis of PD. In this study we investigate the effectiveness of Dynamic Time Warping (DTW) algorithm, which is applied to Archimedean spiral drawings of patients with PD and healthy controls (HC), on PD and healthy subject classification problem. Leave-one-subject-out (LOSO) cross validation scheme is used while training and testing in support vector machine (SVM) and k-nearest neighbors (k-NN) classifiers with various parameters. The accuracy results of %94.44 (%95.83) and %97.52 (%94.44) are achieved by k-NN and SVM classifiers respectively for static (dynamic) spiral test.
Clustered Linked List Forest for IPv6 Lookup
(IEEE, 2013) Erdem, Oguzhan; Carus, Aydin
Providing a high operating frequency and abundant parallelism, Field Programmable Gate Arrays (FPGAs) are the most promising base to realize SRAM-based pipelined architectures for high-speed Internet Protocol (IP) lookup. Owing to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, the existing approaches can hardly accommodate the large and sparsely-distributed IPv6 routing tables. Therefore, memory efficient data structures are recently in high demand. In this paper, clustered linked list forest (CLLF) data structure is proposed for solving the longest prefix matching (LPM) problem in IP lookup. Our structure comprising clustered multiple parallel linked lists achieves significant memory compaction in comparison to the existing approaches. CLLF data structure is implemented on a high throughput SRAM-based parallel and pipelined architecture on FPGAs. Utilizing a state-of-the-art FPGA device, CLLF architecture can accommodate up to 712K IPv6 prefixes while supporting fast incremental routing table updates.
Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs
(IEEE, 2012) Erdem, Oguzhan; Carus, Aydin; Hoang Le
Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. Among all existing implementation platforms, Field Programmable Gate Array (FPGA) is a prevailing platform to implement SRAM-based pipelined architectures for high-speed IP lookup because of its abundant parallelism and other desirable features. However, due to the available on-chip memory and the number of I/O pins of FPGAs, state-of-the-art designs cannot support large routing tables consisting of over 350K prefixes in backbone routers. We propose a search algorithm and data structure denoted Compact Trie (CT) for IP lookup. Our algorithm demonstrates a substantial reduction in the memory footprint compared with the state-of-the-art solutions. A parallel architecture on FPGAs, named Compact Trie Forest (CTF), is introduced to support the data structure. Along with pipelining techniques, our optimized architecture also employs multiple memory banks in each stage to further reduce memory and resource redundancy. Implementation on a state-of-the-art FPGA device shows that the proposed architecture can support large routing tables consisting up to 703K IPv4 or 418K IPv6 prefixes. The post place-and-route result shows that our architecture can sustain a throughput of 420 million lookups per second (MLPS), or 135 Gbps for the minimum packet size of 40 Bytes. The result surpasses the worst-case 150 MLPS required by the standardized 100GbE line cards.
Large-scale SRAM-based IP lookup architectures using compact trie search structures
(Pergamon-Elsevier Science Ltd, 2014) Erdem, Oguzhan; Carus, Aydin; Le, Hoang
SRAM-based pipelined architectures for high-speed IP lookup using Field Programmable Gate Arrays (FPGAs) has recently attracted a great deal of attention from researchers. Due to the limited amount of on-chip memory and the number of I/O pins of FPGAs, compact data structures providing high memory efficiency are in great demand. In IP lookup, a binary trie that is an ordered tree data structure is used to store the routing table entries. In this paper, we propose two compact trie structures denoted Compact Trie Forest (CTF) and Compact Trie(c) (CTc) for Internet Protocol (IP) lookup. The large variant in node sizes leading to the memory inefficiency in hardware implementation is resolved by using multiple disjoint pipelines in CTF. CTc solves the problem within a single pipeline by splitting large nodes into sequentially connected multiple small and fixed size nodes. To support each data structure, two pipelined SRAM-based architectures optimized by allowing multiple memory banks in each stage are also proposed. (C) 2013 Elsevier Ltd. All rights reserved.
MSCCov19Net: multi-branch deep learning model for COVID-19 detection from cough sounds
(Springer Heidelberg, 2023) Ulukaya, Sezer; Sarica, Ahmet Alp; Erdem, Oguzhan; Karaali, Ali
Coronavirus has an impact on millions of lives and has been added to the important pandemics that continue to affect with its variants. Since it is transmitted through the respiratory tract, it has had significant effects on public health and social relations. Isolating people who are COVID positive can minimize the transmission, therefore several exams are proposed to detect the virus such as reverse transcription-polymerase chain reaction (RT-PCR), chest X-Ray, and computed tomography (CT). However, these methods suffer from either a low detection rate or high radiation dosage, along with being expensive. In this study, deep neural network-based model capable of detecting coronavirus from only coughing sound, which is fast, remotely operable and has no harmful side effects, has been proposed. The proposed multi-branch model takes Mel Frequency Cepstral Coefficients (MFCC), Spectrogram, and Chromagram as inputs and is abbreviated as MSCCov19Net. The system is trained on publicly available crowdsourced datasets, and tested on two unseen (used only for testing) clinical and non-clinical datasets. Experimental outcomes represent that the proposed system outperforms the 6 popular deep learning architectures on four datasets by representing a better generalization ability. The proposed system has reached an accuracy of 61.5 % in Virufy and 90.4 % in NoCoCoDa for unseen test datasets.
Multi-pipelined and memory-efficient packet classification engines on FPGAs
(Elsevier Science Bv, 2015) Erdem, Oguzhan; Carus, Aydin
A packet classification task incorporated in network firewalls to recognize and sift threats or unauthorized network accesses is accomplished by checking incoming packet headers against a pre-defined filter set. Plenty of solutions to reduce the memory requirement of filter set storage and accommodate packet classification to line rates have been proposed over the past decade. Among all the existing approaches, hierarchical data structures maintain great memory performance however their hardware realization suffers from two issues: (i) backtracking and (ii) memory inefficiency. In this paper, we propose two data structures denoted range tree-linked list hierarchical search structure (RLHS) and value-coded trie structure with epsilon-branch property (VC epsilon) for packet classification. RLHS resolves backtracking by exploiting range tree in Stage 1 and linked list data structure in Stage 2 overcomes the memory inefficiency. VC epsilon trie that naturally does not involve backtracking problem, solves memory inefficiency issue by comprising a fixed size bin at each node. Apart from conventional binary trie, a new rule is inserted into the first available bin on the path of this rule in a VC epsilon trie, and epsilon-branch property is utilized in case all the bins are full. We also propose a rule categorization algorithm that partitions an input ruleset by considering the field features of rules to minimize the memory requirement. To support the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs). (C) 2015 Elsevier B.V. All rights reserved.
Musical Feature Based Classification of Parkinson's Disease Using Dysphonic Speech
(IEEE, 2018) Kurt, Ilke; Ulukaya, Sezer; Erdem, Oguzhan
Speech and voice disorders are one of the most significant biomarkers in early diagnosis of Parkinson's disease (PD). The development of an objective, reliable and effective prediction model is crucial for the early detection of PD by experts. The aim of this study is to investigate the effectiveness of musical features of voice recordings on PD and healthy subject discrimination issue. Extracted number of 41 musical features from the voice recordings of 28 PD and 62 healthy controls are used in the context of music information retrieval. These features are employed in the classification models either as a single large set or partitioned into smaller feature groups. Leave-one-subject-out (LOSO), leave-one-out (LOO) and 10-fold cross validation schemes are used while training and testing in support vector machine (SVM) and k-nearest neighbors (k-NN) classifiers by providing statistical measures. The effect of low, normal and high tone voice recordings is also studied separately, and the results show that using low-tone voice recordings may not be useful for discrimination of dysphonic voice. Despite using least number of features of all related schemes which use raw voice recordings, our proposed musical features with LOSO cross validation technique perform better accuracy results than the existing studies.
Pipelined Decision Trees for Online Traffic Classification on FPGAs
(Oxford Univ Press, 2023) Erdem, Oguzhan; Soylu, Tuncay; Carus, Aydin
Decision tree (DT)-based machine learning (ML) algorithms are one of the preferred solutions for real-time internet traffic classification in terms of their easy implementation on hardware. However, the rapid increase in today's newly developed applications and the resulting diversity in internet traffic greatly increases the size of DTs. Therefore, the tree-based hardware classifiers cannot keep up with this growth in terms of resource usage and classification speed. To alleviate the problem, we propose to group application classes by certain rules and create an individual small DT per each group. In this article, a pipelined organization of multiple DT data structures, called pipelined decision trees, is proposed as a scalable solution to tree-based traffic classification. We also propose two distinct algorithms, namely confusion matrix-based class aggregation and leaf count-based class aggregation algorithms, to set group creation rules that allows traffic classification on pipelined smaller DTs in a hierarchical order. We further designed an hardware engine on field programmable gate arrays, which can search those pipelined trees within a single clock cycle by transforming them into bit vectors and implementing multiple range comparisons in parallel. Our architecture with 12 classes can run in 928.88 giga bit per second and achieve 96.04% accuracy.
Pipelined hierarchical architecture for high performance packet classification
(Elsevier, 2016) Erdem, Oguzhan
Hierarchical search structures satisfying good memory and update performance demands, are encouraging solution for packet classification in multi-core processors. However, pipelined hardware implementation of these algorithms has two major issues: (1) backtracking which causes stalling the pipeline and (2) memory inefficiency owing to variation in the size of trie nodes. In this paper, we present a clustering algorithm named recursive leaf extraction (RLE) that partitions an input ruleset into a certain number of sub-rulesets to eradicate backtracking in hierarchical search structures. We further enhanced RLE method and proposed Optimized-RLE (O-RLE) algorithm to balance the size of clusters. Additionally, we present a ternary trie data structure (T-epsilon) that takes the advantage of epsilon-branch property to segment large trie nodes into fixed size epsilon-nodes to solve the memory inefficiency problem. We propose two hierarchical data structures denoted Tree-Trie(epsilon) (TT epsilon)and its extended version Tree-Trie(epsilon)-Linked List (TT epsilon L). TT epsilon consists of a binary search tree in Stage 1 and multiple T-epsilon structures in Stage 2. TT epsilon L comprises an additional linked-list (LL) data structure in Stage 3 that maintains the large portion of a nodes and thus freely optimizes search delay with a significant improvement in memory efficiency (20.39 bytes/rule). To accommodate the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs) (134 Gbps). (C) 2016 Elsevier B.V. All rights reserved.
Range Tree-Linked List Hierarchical Search Structure for Packet Classification on FPGAs
(IEEE, 2013) Erdem, Oguzhan; Carus, Aydin
Field Programmable Gate Arrays (FPGAs) satisfying the abundant parallelism and high operating frequency demands are the most promising platform to realize SRAM-based pipelined architectures for high-speed packet classification. Due to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, larger filter databases can hardly be accommodated by the current approaches. Therefore, new data structures which are frugal with the memory are lately in high demand. In this paper, two stage range tree-linked list hierarchical search structure (RLHS) is introduced for packet classification. Our proposed structure comprising range tree in Stage 1 and linked lists in Stage 2, resolves backtracking and memory inefficiency problems in the pipelined hardware implementation of hierarchical search structures. We further present a categorization algorithm that partitions an input ruleset based on the field characteristics of rules to reduce the memory requirement. Each partition has an individual RLHS with specialized node structures free from redundant fields used for storing wildcards and range points. Our design is realized on an SRAM-based parallel and pipelined architecture using FPGAs to achieve high throughput. Utilizing a state-of-the-art FPGA, RLHS architecture can sustain a 404 million packets per second throughput or 129 Gbps (for the minimum packet size of 40 Bytes) while maintaining packet input order and supporting in-place non-blocking rule updates.
Real-Time Traffic Classification using Simple CART Forest on FPGAs
(IEEE, 2018) Soylu, Tuncay; Erdem, Oguzhan; Carus, Aydin; Guner, Edip S.
Traffic classification process categorizes internet traffic into application classes by exploiting packet header data or collected packet statistics. Real-time internet traffic classification is mostly required for network management and security applications. Machine Learning (ML) based traffic classification approaches which utilize statistical properties of traffic flows, have recently attracted great deal of attention from the researches due to its operability under encrypted traffic conditions. In this paper, we propose to use Simple Classification and Regression Trees Forest (SCF) for internet traffic classification. Our proposed scheme comprising multiple parallel trees demonstrates a substantial improvement in search delay and throughput as well as in the memory footprint when compared to a traditional single Simple CART structure. To reach high data rates for real-time classification, we also proposed a parallel and pipelined architecture on Field Programmable Gate Arrays (FPGAs) that support SCF data structure. The post place-and-route FPGA results demonstrate that our design can sustain 854 Gbps or 2669 million classification per second (MCPS) for the minimum packet size of 40 Bytes. Furthermore, our architecture shows an accuracy of 96.6719% for real internet traffic with eight application classes.
Simple CART Based Real-Time Traffic Classification Engine on FPGAs
(IEEE, 2017) Soylu, Tuncay; Erdem, Oguzhan; Carus, Aydin; Guner, Edip S.
Traffic classification is a process which assorts computer network traffic into predefined traffic classes by utilizing packet header information or network packet statistics. Real-time traffic classification is mainly used in network management tasks comprising traffic shaping and flow prioritization as well as in network security applications for intrusion detection. Machine Learning (ML) based traffic classification that exploits statistical characteristics of traffic, has come into prominence recently, due to its ability to cope with encrypted traffic and newly emerging network applications utilizing non-standard ports to circumvent firewalls. To meet high data rates and achieve online classification with ML-based techniques, Field Programmable Gate Arrays (FPGAs) providing abundant parallelism and high operating frequency is the most appropriate platform. In this paper, we propose to use Simple Classification and Regression Trees (Simple CART) machine learning algorithm for traffic classification. However, the variations in node sizes of Simple CART decision tree caused by discretization pre-process incur memory and resource inefficiency problems when the tree is directly mapped onto the hardware. To resolve these problems, we propose to represent Simple CART decision tree by two stage hybrid data structure (Extended-Simple CART) that comprises multiple range trees in Stage 1 and a Simple CART decision tree enriched with bitmaps at its nodes in Stage 2. Our design is implemented on parallel and pipelined architectures using Field Programmable Gate Arrays (FPGAs) to acquire high throughput. Extended-Simple CART architecture can sustain 557 Gbps or 1741 million classification per second (MCPS) (for the minimum packet size of 40 Bytes) on a state-of-the-art FPGA and achieve an accuracy of 96.8% while classifying an internet traffic trace including eight application classes.
Tree-based string pattern matching on FPGAs
(Pergamon-Elsevier Science Ltd, 2016) Erdem, Oguzhan
Network intrusion detection systems (NIDSs) monitor Internet Protocol (IP) traffic to detect anomalous and malicious activities on a network. Despite the plethora of studies in this field, hardware-based string matching engines that can accommodate the advancements in optical networking technology are still in high demand. Furthermore, memory efficient data structures to store intrusion patterns have recently received a great deal of research attention. In this paper, we introduce a tree-based pattern matching (TPM) scheme that comprises a forest of Binary Search Tree (BST) data structures and an accommodating high-throughput multi-pipelined architecture for scalable string matching on hardware. To improve the resource efficiency in hardware implementations, we enhanced TPM scheme (extended-TPM) with two novel tree structures, namely BST-epsilon (BST epsilon) and hierarchical BST (H-BST). Our entire design accomplishes a memory efficiency of 1.07 bytes/char for the latest Snort dictionary. Utilizing a state-of-the-art Field Programmable Gate Arrays (FPGAs), TPM architecture can sustain a throughput of 2.7 Gbps. (C) 2015 Elsevier Ltd. All rights reserved.
Value-Coded Trie Structure for High-Performance IPv6 Lookup
(Oxford Univ Press, 2015) Erdem, Oguzhan; Carus, Aydin; Le, Hoang
Dynamically updateable and memory-efficient search structures for Internet protocol (IP) lookup have lately attracted a great deal of attention from the researchers. In this paper, we focus on the next-generation IPv6 routing protocol comprising large and sparsely distributed routing tables. The existing data structures either suffer from inefficient resource and memory usage (trie-based algorithms), or require complicated construction processes such as converting routing prefixes into their longer representatives and sorting (tree-based algorithms), or both. We propose a novel data structure denoted value-coded trie (VC-trie) for IP lookup. VC-trie provides significant memory saving in comparison with that of the existing solutions in both IPv4 and IPv6 domains. Thereby, our structure can support longer prefix lengths and larger routing tables. We also design an static random access memory (SRAM)-based pipelined architecture to assist the VC-trie structure to improve the throughput. The architecture is implemented utilizing a state-of-the-art field programmable gate array (FPGA) device and sustainable throughput of 448 million lookups per second (with a routing table consisting of 324K prefixes) is achieved. Furthermore, the architecture can be enhanced with external SRAMs to relax the limitations of the existing FPGA device in on-chip memory.

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