Yazar "Cini, Ugur" seçeneğine göre listele

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    An alternative carry-save arithmetic for new generation field programmable gate arrays
    (Tubitak Scientific & Technological Research Council Turkey, 2016) Cini, Ugur; Aktan, Mustafa; Morgul, Avni
    In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.
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    Dual-mode OTA based biquadratic filter suitable for current-mode applications
    (Elsevier Gmbh, Urban & Fischer Verlag, 2017) Cini, Ugur; Aktan, Mustafa
    In this paper, a dual mode single-input multiple-output (SIMO) biquadratic filter structure is presented using multi-output Operational Transconductance Amplifiers (OTAs). Using a simple switch, the filter operates alternatively in trans-admittance mode or current mode. Selection of working mode using a switch provides flexibility for current-mode design. The filter natural angular frequency (coo) and quality factor (Q) can be orthogonally adjusted both in current mode and trans-admittance mode operation. The proposed structure has simple structure, requiring only four OTAs and two grounded capacitors. The proposed structure is the only SIMO structure where the working mode is selected using a switch. The proposed biquadratic structure is realized using 0.35 mu m CMOS technology, and, circuit functionality is verified by SPICE simulations. (C) 2017 Elsevier GmbH. All rights reserved.
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    DVCC-based very low-offset current-mode instrumentation amplifier
    (Taylor & Francis Ltd, 2017) Cini, Ugur; Toker, Ali
    This paper presents an alternative implementation of a chopper-modulated current-mode instrumentation amplifier. The structure provides very low-offset voltage at the output due to chopper modulation and residual offset removal path. The residual offset removal path is based on low-pass filtering using grounded capacitances which provides compact design structure compared to various chopper-modulated instrumentation amplifier designs. Rail-to-rail input common-mode range is possible due to transmission gate-based input chopper switching scheme. The design is made using a 0.35-mu m CMOS process with +/- 1.65V supply voltage. The area of the amplifier is 234 mu mx344 mu m, including all the filtering elements. The proposed circuit with residual offset removal path provides less than 1 mu V input referred offset voltage. The advantage of the proposed instrumentation amplifier is its large bandwidth, simple design scheme and compact area compared to chopper-modulated voltage mode amplifiers.
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    AN ENHANCED CURRENT-CONVEYOR BASED INSTRUMENTATION AMPLIFIER WITH HIGH CMRR
    (Istanbul Univ, Fac Engineering, 2017) Cini, Ugur
    In this work, a current-mode instrumentation amplifier with common-mode current cancellation is realized using enhanced CCII topology. Detailed CMRR analysis is performed and parameters for maximizing the CMRR are defined. The proposed structure is simulated using SPICE and realized on a prototyping board. According to the simulation and measurement results the proposed circuit shows superior CMRR performance compared to other well-known current-mode instrument amplifier topologies.
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    A High Gain and Low-Offset Current-Mode Instrumentation Amplifier Using Differential Difference Current Conveyors
    (IEEE, 2015) Cini, Ugur; Arslan, Emre
    In this work, a current-mode high CMRR and low offset instrumentation amplifier is proposed. In the structure, only differential difference current conveyors (DDCC) are employed. The offset of the instrumentation amplifier is suppressed using an integrator feedback stage. The CMRR of the system is simulated using mismatch models for the DDCC elements employed. The CMRR of the instrumentation amplifier is independent of resistor mismatches, and, high CMRR is achieved if good matching of the differential transistors of each current conveyor is provided. The proposed instrumentation amplifier is designed using 0.35 mu m technology and simulated using HSPICE. The designed instrumentation amplifier provides high CMRR with low offset and it is especially suitable for AC coupled measurements. The simplicity of the design structure is the main advantage of the provided design where only DDCC elements are required for high CMRR and high output swing.
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    High Performance FIR Filter Design for 6-input LUT Based FPGAs
    (IEEE, 2015) Cini, Ugur; Aktan, Mustafa
    Advanced FPGA structures contain 6-input LUT tables suitable for the implementation of complex logic functions in a more compact structure. In this paper, high performance fixed coefficient FIR filters are designed by exploiting the advantages of 6-input LUT structures. Using the proposed methodology, fixed coefficient multiplication and accumulation is employed as only two cascades of 6-input LUTs in the critical path. Therefore high performance FIR filtering is possible without any pipelining in the system. For the multiply-accumulate operations only (6, 3) counters are employed together with redundant carry double save operations. 440 MHz clock frequency is reached for the designed 25 tap FIR filter on the Stratix II family FPGA. The proposed arithmetic structure provides more than 90% speed advantage over hardware multiplier based multiply accumulate operations.
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    A High Performance Multiply-Accumulate Unit with Double Carry-Save Scheme for 6-Input LUT Based Reconfigurable Systems
    (IEEE, 2015) Cini, Ugur; Kurt, Olcay
    Redundant number systems provide carry-propagation free arithmetic, so that faster arithmetic circuits can be designed. In this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed especially suitable for 6-input look-up-table (LUT) based FPGAs. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of logic depth is provided which results as high performance without any pipeline requirement in the system. The proposed MAC unit has 16x16 input with sign extended 40-bit output. The MAC unit is compared to conventional redundant carry-save and various standard MAC architectures. The proposed structure provides highest performance among the structures that have been compared.
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    Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems
    (Kaunas Univ Technology, 2017) Cini, Ugur; Kocyigit, Gokhan
    Counter and compressor arrays are frequently employed in multiplier design to efficiently reduce partial products in VLSI design. On the other hand, in reconfigurable systems, fast carry chains boost the performance of carry-propagate adders. So that, in reconfigurable systems, to save logic element area, counter and compressor trees are not employed as much since they require more area than carry-propagate scheme. In this work, carry-propagate multi-operand adders are employed in smaller blocks and the outputs are merged using double carry-save encoding to increase performance in reconfigurable systems. Hence, a more compact structure is achieved, compared to full redundant partial product reduction scheme providing comparable speed performance with counter array based carry-save structure. To show the effectiveness of the implementation, fused multiply-accumulate ( MAC) units are designed for various bit-widths. The structure is implemented on Altera (TM) Stratix III and Cyclone III FPGAs and the results show that, using least depth of pipeline, the throughput is better than regular carry-propagate and fully redundant carry-save reduction schemes.
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    A Low-Offset High CMRR Current-Mode Instrumentation Amplifier Using Differential Difference Current Conveyor
    (IEEE, 2014) Cini, Ugur
    Current-mode circuits are generally desirable for their high bandwidth. Moreover, current-mode instrumentation amplifiers have an advantage over voltage-mode counterparts that, they do not require precise resistor matching for a high CMRR. In this work, a current-mode instrumentation amplifier is proposed by employing Differential Difference Current Conveyor (DDCC). The proposed structure employs a single DDCC element, and an operational amplifier is used as a buffer or a final amplifier stage. After the explanation of the circuit, redundant output feedback (ROFB) circuit is presented to increase CMRR and to overcome the offset voltage at the output of the DDCC. The DDCC element is designed with 0.35 mu m technology and the proposed circuits are simulated using HSPICE. The proposed circuit with the feedback path provides more than 110 dB CMRR value at 1 MHz which is much higher than other current-mode implementations.
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    MAC Unit for Reconfigurable Systems Using Multi-Operand Adders with Double Carry-Save Encoding
    (IEEE, 2016) Cini, Ugur; Kurt, Olcay
    In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16x16-bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on AlteraTM Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiply-accumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.
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    A MAC Unit with Double Carry-Save Scheme Suitable for 6-Input LUT Based Reconfigurable Systems
    (IEEE, 2015) Cini, Ugur; Kurt, Olcay
    In this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed. The design utilizes double carry-save output encoding. The structure is especially suitable for 6-input LUT based reconfigurable systems. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of logic depth is provided which results as high performance without any pipeline in the system. The proposed system is not affected by carry propagation because of redundant arithmetic scheme implemented in the MAC structure. Designed MAC unit has 16x16-bit multiplier and 40-bit accumulate output. It is synthesized on Altera (TM) Stratix III FPGAs and provides better performance compared to conventional pipelined carry-propagate multiply-accumulate units.
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    On the Efficient Implementation of Pulse-Width Modulated Digital Analog Converters
    (Gazi Univ, 2017) Cini, Ugur
    Pulse-Width Modulated Digital-Analog Converter (PWM DAC) is the most popular digital-analog conversion structure in embedded system design. However, there is no explicit formulation existing in the literature for the efficient utilization of PWM DAC implementation regarding to resolution and switching noise considerations. In this paper, optimum PWM frequency formulization is given to limit switching noise less than the least significant bit in the implemented DAC structure. So that, PWM resolution is maximized regarding to the analog signal bandwidth, where analog bandwidth and switching noise are the tradeoff in the PWM DAC. In addition, to extend the limits of the PWM modulator, a hybrid R-2R and PWM structure is proposed for the resolution improvement, resulting as higher dynamic range for the total system.