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Öğe Bit vector-coded simple CART structure for low latency traffic classification on FPGAs(Elsevier, 2020) Soylu, Tuncay; Erdem, Oguzhan; Carus, AydinTraffic classification is the determination of the application types during real-time flow of internet traffic. Machine learning (ML) based classification approaches that can classify internet traffic using statistical properties of flows are of great interest, due to its ability to work under encrypted traffic conditions. In this paper, we propose a novel data structure, named Bit Vector Coded Simple CART (BC-SC), for ML based internet traffic classification. BC-SC data structure is a scalable solution in terms of the number of application classes while providing a significant improvement in search latency, memory requirement and throughput when compared to the state-of-the-art approaches. We also designed two alternative hardware architectures, namely Pipelined and Discrete Parallel Range Comparators (DPRC)-based, on the Field Programmable Gate Array (FPGA) platform to support BC-SC data structure. Pipelined and DPRC-based architectures can achieve up to 665 and 914 giga bit per second (Gbps) or 2078 and 2857 million classifications per second (MCPS) respectively for the minimum packet size of 40 Byte. Furthermore, the proposed engines both can reach 96.8125% accuracy with eight application classes. (C) 2019 Elsevier B.V. All rights reserved.Öğe Clustered Linked List Forest for IPv6 Lookup(IEEE, 2013) Erdem, Oguzhan; Carus, AydinProviding a high operating frequency and abundant parallelism, Field Programmable Gate Arrays (FPGAs) are the most promising base to realize SRAM-based pipelined architectures for high-speed Internet Protocol (IP) lookup. Owing to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, the existing approaches can hardly accommodate the large and sparsely-distributed IPv6 routing tables. Therefore, memory efficient data structures are recently in high demand. In this paper, clustered linked list forest (CLLF) data structure is proposed for solving the longest prefix matching (LPM) problem in IP lookup. Our structure comprising clustered multiple parallel linked lists achieves significant memory compaction in comparison to the existing approaches. CLLF data structure is implemented on a high throughput SRAM-based parallel and pipelined architecture on FPGAs. Utilizing a state-of-the-art FPGA device, CLLF architecture can accommodate up to 712K IPv6 prefixes while supporting fast incremental routing table updates.Öğe Compact Trie Forest: Scalable architecture for IP Lookup on FPGAs(IEEE, 2012) Erdem, Oguzhan; Carus, Aydin; Hoang LeMemory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. Among all existing implementation platforms, Field Programmable Gate Array (FPGA) is a prevailing platform to implement SRAM-based pipelined architectures for high-speed IP lookup because of its abundant parallelism and other desirable features. However, due to the available on-chip memory and the number of I/O pins of FPGAs, state-of-the-art designs cannot support large routing tables consisting of over 350K prefixes in backbone routers. We propose a search algorithm and data structure denoted Compact Trie (CT) for IP lookup. Our algorithm demonstrates a substantial reduction in the memory footprint compared with the state-of-the-art solutions. A parallel architecture on FPGAs, named Compact Trie Forest (CTF), is introduced to support the data structure. Along with pipelining techniques, our optimized architecture also employs multiple memory banks in each stage to further reduce memory and resource redundancy. Implementation on a state-of-the-art FPGA device shows that the proposed architecture can support large routing tables consisting up to 703K IPv4 or 418K IPv6 prefixes. The post place-and-route result shows that our architecture can sustain a throughput of 420 million lookups per second (MLPS), or 135 Gbps for the minimum packet size of 40 Bytes. The result surpasses the worst-case 150 MLPS required by the standardized 100GbE line cards.Öğe An Expert System for Determining the Emotional Change on a Critical Event Using Handwriting Features(Uikten - Assoc Information Communication Technology Education & Science, 2016) Ugurlu, Bora; Kandemir, Rembiye; Carus, Aydin; Abay, ErcanAn individual may sometimes feel anxious when a critical event happens. Job interview, wedding, moving in a new city/country can result this occurrence. Examinations taken in school are also that kind of events. Since our handwriting is controlled by brain, it is possible to see clear changes in handwriting style during examinations. In our study, an expert system is developed which considers handwriting features to predict student's exam anxiety state. 210 handwriting samples are collected and classification is made by using J48 decision tree algorithm. The average of Precision, Recall and F-Measure metrics are 71%, 66% and 67%, respectively.Öğe ISSDC DIGRAM CODING BASED LOSSLESS DATA COMPRESSION ALGORITHM(Slovak Acad Sciences Inst Informatics, 2010) Mesut, Altan; Carus, AydinIn this paper, a new lossless data compression method that is based on digram coding is introduced This data compression method uses semi-static dictionaries All of the used characters and most frequently used two character blocks (digrams) in the source are found and inserted into a dictionary in the first pass, compression is performed in the second pass This two-pass structure is repeated several times and in every iteration particular number of elements is inserted in the dictionary until the dictionary is filled This algorithm (ISSDC Iterative Semi-Static Digram Coding) also includes some mechanisms that can decide about total number of iterations and dictionary size whenever these values are not given by the user Our experiments show that ISSDC is better than LZW/GIF and BPE in compression ratio It is worse than DEFLATE in compression of text and binary data, but better than PNG (which uses DEFLATE compression) in lossless compression of simple imagesÖğe Large-scale SRAM-based IP lookup architectures using compact trie search structures(Pergamon-Elsevier Science Ltd, 2014) Erdem, Oguzhan; Carus, Aydin; Le, HoangSRAM-based pipelined architectures for high-speed IP lookup using Field Programmable Gate Arrays (FPGAs) has recently attracted a great deal of attention from researchers. Due to the limited amount of on-chip memory and the number of I/O pins of FPGAs, compact data structures providing high memory efficiency are in great demand. In IP lookup, a binary trie that is an ordered tree data structure is used to store the routing table entries. In this paper, we propose two compact trie structures denoted Compact Trie Forest (CTF) and Compact Trie(c) (CTc) for Internet Protocol (IP) lookup. The large variant in node sizes leading to the memory inefficiency in hardware implementation is resolved by using multiple disjoint pipelines in CTF. CTc solves the problem within a single pipeline by splitting large nodes into sequentially connected multiple small and fixed size nodes. To support each data structure, two pipelined SRAM-based architectures optimized by allowing multiple memory banks in each stage are also proposed. (C) 2013 Elsevier Ltd. All rights reserved.Öğe Multi-pipelined and memory-efficient packet classification engines on FPGAs(Elsevier Science Bv, 2015) Erdem, Oguzhan; Carus, AydinA packet classification task incorporated in network firewalls to recognize and sift threats or unauthorized network accesses is accomplished by checking incoming packet headers against a pre-defined filter set. Plenty of solutions to reduce the memory requirement of filter set storage and accommodate packet classification to line rates have been proposed over the past decade. Among all the existing approaches, hierarchical data structures maintain great memory performance however their hardware realization suffers from two issues: (i) backtracking and (ii) memory inefficiency. In this paper, we propose two data structures denoted range tree-linked list hierarchical search structure (RLHS) and value-coded trie structure with epsilon-branch property (VC epsilon) for packet classification. RLHS resolves backtracking by exploiting range tree in Stage 1 and linked list data structure in Stage 2 overcomes the memory inefficiency. VC epsilon trie that naturally does not involve backtracking problem, solves memory inefficiency issue by comprising a fixed size bin at each node. Apart from conventional binary trie, a new rule is inserted into the first available bin on the path of this rule in a VC epsilon trie, and epsilon-branch property is utilized in case all the bins are full. We also propose a rule categorization algorithm that partitions an input ruleset by considering the field features of rules to minimize the memory requirement. To support the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs). (C) 2015 Elsevier B.V. All rights reserved.Öğe A new compression algorithm for fast text search(Tubitak Scientific & Technological Research Council Turkey, 2016) Carus, Aydin; Mesut, AltanWe propose a new compression algorithm that compresses plain texts by using a dictionary-based model and a compressed string-matching approach that can be used with the compressed texts produced by this algorithm. The compression algorithm (CAFTS) can reduce the size of the texts to approximately 41% of their original sizes. The presented compressed string matching approach (SoCAFTS), which can be used with any of the known pattern matching algorithms, is compared with a powerful compressed string matching algorithm (ETDC) and a compressed string-matching tool (Lzgrep). Although the search speed of ETDC is very good in short patterns, it can only search for exact words and its compression performance differs from one natural language to another because of its word-based structure. Our experimental results show that SoCAFTS is a good solution when it is necessary to search for long patterns in a compressed document.Öğe A new word-based compression model allowing compressed pattern matching(Tubitak Scientific & Technological Research Council Turkey, 2017) Bulus, Halil Nusret; Carus, Aydin; Mesut, AltanIn this study a new semistatic data compression model that has a fast coding process and that allows compressed pattern matching is introduced. The name of the proposed model is chosen as tagged word-based compression algorithm (TWBCA) since it has a word-based coding and word-based compressed matching algorithm. The model has two phases. In the first phase a dictionary is constructed by adding a phrase, paying attention to word boundaries, and in the second phase compression is done by using codewords of phrases in this dictionary. The first byte of the codeword determines whether the word is compressed or not. By paying attention to this rule, the CPM process can be conducted as word based. In addition, the proposed method makes it possible to also search for the group of consecutively compressed words. Any of the previous pattern matching algorithms can be chosen to use in compressed pattern matching as a black box. The duration of the CPM process is always less than the duration of the same process on the texts coded by Gzip tool. While matching longer patterns, compressed pattern matching takes more time on the texts coded by compress and end-tagged dense code (ETDC). However, searching shorter patterns takes less time on texts coded by our approach than the texts compressed with compress. Besides this, the compression ratio of our algorithm has a better performance against ETDC only on a file that has been written in Turkish. The compression performance of TWBCA is stable and does not vary over 6% on different text files.Öğe On Class Numbers of Real Quadratic Fields with Certain Fundamental Discriminants(European Journal Pure & Applied Mathematics, 2015) Pekin, Ayten; Carus, AydinLet N denote the sets of positive integers and D is an element of N be square free, and let chi(D), h = h (D) denote the non-trivial Dirichlet character, the class number of the real quadratic field K = Q (root D), respectively. Ono proved the theorem in [2] by applying Sturm's Theorem on the congruence of modular form to Cohen's half integral weight modular forms. Later, Dongho Byeon proved a theorem and corollary in [1] by refining Ono's methods. In this paper, we will give a theorem for certain real quadratic fields by considering above mentioned studies. To do this, we shall obtain an upper bound different from current bounds for L(1, chi(D)) and use Dirichlet's class number formula.Öğe Performance Comparison of JPEG, JPEG2000 & JPEG XR Image Compression Standards(IEEE, 2016) Ozturk, Emir; Mesut, Altan; Carus, AydinIn this study, the performances of JPEG (the most widely used lossy image compression standard until it was published in 1992), JPEG2000 (designed to provide superior image quality at low bit rates) and JPEG XR (aimed to reach the speed of JPEG and the quality of JPEG2000) are evaluated with an application developed in C# language which is able to use different codecs. The results show that recently developed JPEG standard (JPEG XR) is able to compress images with the same quality as JPEG2000, but not the same speed as JPEG.Öğe Pipelined Decision Trees for Online Traffic Classification on FPGAs(Oxford Univ Press, 2023) Erdem, Oguzhan; Soylu, Tuncay; Carus, AydinDecision tree (DT)-based machine learning (ML) algorithms are one of the preferred solutions for real-time internet traffic classification in terms of their easy implementation on hardware. However, the rapid increase in today's newly developed applications and the resulting diversity in internet traffic greatly increases the size of DTs. Therefore, the tree-based hardware classifiers cannot keep up with this growth in terms of resource usage and classification speed. To alleviate the problem, we propose to group application classes by certain rules and create an individual small DT per each group. In this article, a pipelined organization of multiple DT data structures, called pipelined decision trees, is proposed as a scalable solution to tree-based traffic classification. We also propose two distinct algorithms, namely confusion matrix-based class aggregation and leaf count-based class aggregation algorithms, to set group creation rules that allows traffic classification on pipelined smaller DTs in a hierarchical order. We further designed an hardware engine on field programmable gate arrays, which can search those pipelined trees within a single clock cycle by transforming them into bit vectors and implementing multiple range comparisons in parallel. Our architecture with 12 classes can run in 928.88 giga bit per second and achieve 96.04% accuracy.Öğe Range Tree-Linked List Hierarchical Search Structure for Packet Classification on FPGAs(IEEE, 2013) Erdem, Oguzhan; Carus, AydinField Programmable Gate Arrays (FPGAs) satisfying the abundant parallelism and high operating frequency demands are the most promising platform to realize SRAM-based pipelined architectures for high-speed packet classification. Due to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, larger filter databases can hardly be accommodated by the current approaches. Therefore, new data structures which are frugal with the memory are lately in high demand. In this paper, two stage range tree-linked list hierarchical search structure (RLHS) is introduced for packet classification. Our proposed structure comprising range tree in Stage 1 and linked lists in Stage 2, resolves backtracking and memory inefficiency problems in the pipelined hardware implementation of hierarchical search structures. We further present a categorization algorithm that partitions an input ruleset based on the field characteristics of rules to reduce the memory requirement. Each partition has an individual RLHS with specialized node structures free from redundant fields used for storing wildcards and range points. Our design is realized on an SRAM-based parallel and pipelined architecture using FPGAs to achieve high throughput. Utilizing a state-of-the-art FPGA, RLHS architecture can sustain a 404 million packets per second throughput or 129 Gbps (for the minimum packet size of 40 Bytes) while maintaining packet input order and supporting in-place non-blocking rule updates.Öğe Real-Time Traffic Classification using Simple CART Forest on FPGAs(IEEE, 2018) Soylu, Tuncay; Erdem, Oguzhan; Carus, Aydin; Guner, Edip S.Traffic classification process categorizes internet traffic into application classes by exploiting packet header data or collected packet statistics. Real-time internet traffic classification is mostly required for network management and security applications. Machine Learning (ML) based traffic classification approaches which utilize statistical properties of traffic flows, have recently attracted great deal of attention from the researches due to its operability under encrypted traffic conditions. In this paper, we propose to use Simple Classification and Regression Trees Forest (SCF) for internet traffic classification. Our proposed scheme comprising multiple parallel trees demonstrates a substantial improvement in search delay and throughput as well as in the memory footprint when compared to a traditional single Simple CART structure. To reach high data rates for real-time classification, we also proposed a parallel and pipelined architecture on Field Programmable Gate Arrays (FPGAs) that support SCF data structure. The post place-and-route FPGA results demonstrate that our design can sustain 854 Gbps or 2669 million classification per second (MCPS) for the minimum packet size of 40 Bytes. Furthermore, our architecture shows an accuracy of 96.6719% for real internet traffic with eight application classes.Öğe Simple CART Based Real-Time Traffic Classification Engine on FPGAs(IEEE, 2017) Soylu, Tuncay; Erdem, Oguzhan; Carus, Aydin; Guner, Edip S.Traffic classification is a process which assorts computer network traffic into predefined traffic classes by utilizing packet header information or network packet statistics. Real-time traffic classification is mainly used in network management tasks comprising traffic shaping and flow prioritization as well as in network security applications for intrusion detection. Machine Learning (ML) based traffic classification that exploits statistical characteristics of traffic, has come into prominence recently, due to its ability to cope with encrypted traffic and newly emerging network applications utilizing non-standard ports to circumvent firewalls. To meet high data rates and achieve online classification with ML-based techniques, Field Programmable Gate Arrays (FPGAs) providing abundant parallelism and high operating frequency is the most appropriate platform. In this paper, we propose to use Simple Classification and Regression Trees (Simple CART) machine learning algorithm for traffic classification. However, the variations in node sizes of Simple CART decision tree caused by discretization pre-process incur memory and resource inefficiency problems when the tree is directly mapped onto the hardware. To resolve these problems, we propose to represent Simple CART decision tree by two stage hybrid data structure (Extended-Simple CART) that comprises multiple range trees in Stage 1 and a Simple CART decision tree enriched with bitmaps at its nodes in Stage 2. Our design is implemented on parallel and pipelined architectures using Field Programmable Gate Arrays (FPGAs) to acquire high throughput. Extended-Simple CART architecture can sustain 557 Gbps or 1741 million classification per second (MCPS) (for the minimum packet size of 40 Bytes) on a state-of-the-art FPGA and achieve an accuracy of 96.8% while classifying an internet traffic trace including eight application classes.Öğe SOME RESULTS ON THE CLASS NUMBERS OF CERTAIN REAL QUADRATIC FIELDS(Pushpa Publishing House, 2009) Pekin, Ayten; Carus, AydinIn this paper, we revisit the relations between the fundamental units' coefficients of the real quadratic fields K = Q(root D) and convergents of the continued fraction expansions of W-D. Furthermore, we provide a theorem and obtain some new results on the class numbers of K = Q(root D) by using solvability of the equation x(2) - Dy-2 = sigma(2) and the relations mentioned above.Öğe Value-Coded Trie Structure for High-Performance IPv6 Lookup(Oxford Univ Press, 2015) Erdem, Oguzhan; Carus, Aydin; Le, HoangDynamically updateable and memory-efficient search structures for Internet protocol (IP) lookup have lately attracted a great deal of attention from the researchers. In this paper, we focus on the next-generation IPv6 routing protocol comprising large and sparsely distributed routing tables. The existing data structures either suffer from inefficient resource and memory usage (trie-based algorithms), or require complicated construction processes such as converting routing prefixes into their longer representatives and sorting (tree-based algorithms), or both. We propose a novel data structure denoted value-coded trie (VC-trie) for IP lookup. VC-trie provides significant memory saving in comparison with that of the existing solutions in both IPv4 and IPv6 domains. Thereby, our structure can support longer prefix lengths and larger routing tables. We also design an static random access memory (SRAM)-based pipelined architecture to assist the VC-trie structure to improve the throughput. The architecture is implemented utilizing a state-of-the-art field programmable gate array (FPGA) device and sustainable throughput of 448 million lookups per second (with a routing table consisting of 324K prefixes) is achieved. Furthermore, the architecture can be enhanced with external SRAMs to relax the limitations of the existing FPGA device in on-chip memory.