Yazar "Aktan, Mustafa" seçeneğine göre listele

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    An alternative carry-save arithmetic for new generation field programmable gate arrays
    (Tubitak Scientific & Technological Research Council Turkey, 2016) Cini, Ugur; Aktan, Mustafa; Morgul, Avni
    In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.
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    Dual-mode OTA based biquadratic filter suitable for current-mode applications
    (Elsevier Gmbh, Urban & Fischer Verlag, 2017) Cini, Ugur; Aktan, Mustafa
    In this paper, a dual mode single-input multiple-output (SIMO) biquadratic filter structure is presented using multi-output Operational Transconductance Amplifiers (OTAs). Using a simple switch, the filter operates alternatively in trans-admittance mode or current mode. Selection of working mode using a switch provides flexibility for current-mode design. The filter natural angular frequency (coo) and quality factor (Q) can be orthogonally adjusted both in current mode and trans-admittance mode operation. The proposed structure has simple structure, requiring only four OTAs and two grounded capacitors. The proposed structure is the only SIMO structure where the working mode is selected using a switch. The proposed biquadratic structure is realized using 0.35 mu m CMOS technology, and, circuit functionality is verified by SPICE simulations. (C) 2017 Elsevier GmbH. All rights reserved.
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    High Performance FIR Filter Design for 6-input LUT Based FPGAs
    (IEEE, 2015) Cini, Ugur; Aktan, Mustafa
    Advanced FPGA structures contain 6-input LUT tables suitable for the implementation of complex logic functions in a more compact structure. In this paper, high performance fixed coefficient FIR filters are designed by exploiting the advantages of 6-input LUT structures. Using the proposed methodology, fixed coefficient multiplication and accumulation is employed as only two cascades of 6-input LUTs in the critical path. Therefore high performance FIR filtering is possible without any pipelining in the system. For the multiply-accumulate operations only (6, 3) counters are employed together with redundant carry double save operations. 440 MHz clock frequency is reached for the designed 25 tap FIR filter on the Stratix II family FPGA. The proposed arithmetic structure provides more than 90% speed advantage over hardware multiplier based multiply accumulate operations.